Event Details Location: DoubleTree by Hilton, San Jose, CA Time: 8:30 - 6:00 PDTAdmission: RISC-V CON is free to attend Registration: visit the event website About Andes Technology As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V. Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 16 billion Andes-powered SoCs are driving innovations globally. Discover more at connect with Andes on LinkedIn, X , and YouTube.
San Jose, CA, April 02, 2025 (GLOBE NEWSWIRE) -- Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, proudly announces the Silicon Valley 2025 Andes RISC-V CON scheduled for April 29, 2025. The in-person event will gather industry leaders, innovators, and developers to explore the latest advancements in RISC-V technology and celebrate Andes Technology’s two decades of groundbreaking innovation.
Fireside chat: What’s coming in AI? – Facilitated by Charlie Cheng, Andes, Board Advisor with keynotes from: Jeff Bier, Founder, Edge AI and Embedded Vision AlliancePete Warden, Founder & CEO, Useful Sensors Developer Track – Hands-on Technical Training (Limited Seating! ) For engineers looking to gain practical insights, the Developer Track offers four in-depth sessions designed to provide hands-on experience with cutting-edge RISC-V concepts and system optimization.
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